Silicon Physical Design Engineer
Axelera AI / Eindhoven (NL)Apply on site
Axelera AI is a truly European deep-tech Start Up company which is developing a game-changing hardware and software platform for AI at the edge that will make the industry more integrated, efficient and accessible. Our mission is to spread artificial intelligence for a green, fair, trusted and safe world enabling new application of AI in diverse sectors like smart cities, retail and other markets. Our company is a spin-off from a multinational deep-tech group and is backed by a strong syndicate of institutional investors. We have an extraordinary and international team of top talented researchers and developers working in the headquarter in Eindhoven (NL) and in the branch offices in Leuven (BE), Zurich (CH) and Pisa (IT).
You will have demonstrable skills in ASIC Physical Design, from RTL to GDS, including hands-on expertise in building physical design partitions from synthesis to place and route through all sign-off including timing signoff, physical verification, EMIR signoff, and formal verification. You will have the ability to work closely with architecture/RTL teams to build successful and on-time physical partitions.
Essential skills (/ Minimum requirements)
- 10+ years of experience in Physical Design.
- Great communication and teamwork to contribute to diverse and inclusive teams.
- Proven track record of implementing designs through synthesis, Floorplanning, place and route, extraction, timing, and physical verification.
- Understanding of constraints generation, STA, timing optimization, and timing closure.
- Experience in EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Calibre.
- Proficient understanding of CTS and different clock building techniques
- Experience in IP integration (memories, IO's, embedded processors, double data rate, networking fabrics, and Analog IP)
- Scripting skills in Python, Tcl, or Perl
- Outstanding technical problem solving and debugging ability
- Fluent in English, both in speaking and writing
Desirable Experience and skills
- Expertise in chip top-level integration, I/O ring design, ESD and latch-up methodologies
- Experience interfacing with packaging team and performing chip-package-board co-simulation
- Influence tools, flows, and overall design methodology in design construction, signoff, and optimization
- Ability to collaborate and work directly with the tool vendors, and drive them to resolve tools bugs, as well as implement the required improvements
- Knowledge of semiconductor device physics and transistor characteristics
- Experience with multi-clock, multi-power-domain design
- Continuous integration methodology, architecting regression test-suites
- Setting up processes and checks for receiving releases from IP vendors and providing IP releases to internal teams
- Able to work autonomously and plan and perform research tasks
- You have a strong sense of responsibility and want to "Make the impossible possible"
Conditions and benefits
Take the chance to become part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.
An open culture that not only supports creativity and continual innovation is awaiting you.
Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.
Great! We are looking forward to receiving your application! For any further questions or information, please feel free to contact Heike Wilfling, HR Business Partner, email@example.com. For further information on Axelera AI please also have a look on our website: www.axelera.ai